In recent years, development has been underway for a semiconductor device including a ferroelectric capacitor (Ferroelectric Random Access Memory: hereinafter referred to as “FeRAM”) which stores information utilizing hysteresis characteristics of ferroelectrics. FeRAM is a nonvolatile memory which does not lose information even after being powered off, and has advantageous characteristics that it can achieve high degree of integration, high speed drive, high durability and low power consumption. A ferroelectric capacitor used in FeRAM has a structure in which a pair of electrodes sandwiches a film (ferroelectric film) made of a ferroelectric oxide, such as PZT (Pb(Zr, Ti)O3) or SBT (SrBi2Ta2O9), having a large residual polarization quantity.
FIGS. 1A to 1I are schematic sectional views depicting, in process sequence, one example of a related method of manufacturing FeRAM.
First, as depicted in FIG. 1A, after a transistor (not depicted) is formed on a semiconductor substrate (not depicted), an interlayer insulation film 11 covering the transistor is formed and an SiN film 12 is formed on the interlayer insulation film 11. Then, a contact hole running from a surface of the SiN film 12 to the transistor is formed using a photolithographic method, and a plug 13 is formed by embedding W (tungsten) in the contact hole.
Then, as depicted in FIG. 1B, a lower electrode film 14 made of Ir (Iridium), a ferroelectric film (PZT film) 15, and an upper electrode film 16 made of IrOx (iridium oxide) are formed on the SiN film 12 and the plug 13. Then, as depicted in FIG. 1C, a Pt (platinum) film 17, which acts as a cap layer, is formed on the upper electrode film 16. Incidentally, although the cap layer is herein provided on the upper electrode film 16, the cap layer is not provided in some cases.
Next, as depicted in FIG. 1D, a TiN film 18 is formed on the Pt film 17 and then a SiO2 film (TEOS (Tetra-Ethyl-Ortho-Silicate) film) 19 is formed on the TiN film 18. Then, as depicted in FIG. 1E, a photoresist film 20 is formed on the SiO2 film 19, and this photoresist film 20 is patterned into a predetermined shape.
After that, as depicted in FIG. 1F, the SiO2 film 19 is etched with the photoresist film 20 as a mask. Then, as depicted in FIG. 1G, after the TiN film 18 is etched, the photoresist film 20 is removed.
Subsequently, as depicted in FIG. 1H, the Pt film 17, the upper electrode film 16, the ferroelectric film 15, and the lower electrode film 14 are collectively etched with the remaining SiO2 film 19 and TiN film 18 as a hard mask. With this, a ferroelectric capacitor 25 having a structure in which the ferroelectric film 15 is sandwiched between the lower electrode film 14 and the upper electrode film 16 is formed. Thereafter, as depicted in FIG. 1I, the hard mask (the SiO2 film 19 and the TiN film 18) is removed by dry etching and wet etching. Thus, a semiconductor device including the ferroelectric capacitor 25 is completed.
In this regard, when stack type ferroelectric capacitors are manufactured, the upper electrode film 16 to the lower electrode film 14 (the cap layer to the lower electrode film, if there is any cap layer) are collectively etched as depicted in FIGS. 1A to 1I. A semiconductor substrate is heated to high temperature (400° C., for example) to improve reactivity during the collective etching, and becomes susceptible to oxidation. The upper electrode film 16 and the lower electrode film 14 are exposed to high temperature also in a crystallization process and a recovery anneal process of the ferroelectric film. This is a reason why materials for the upper electrode film 16 and the lower electrode film 14 are required to have nonoxidizing properties or conductive properties that do not deteriorate even if the materials are oxidized. Thus, noble metals such as Ir are used as described above. However, since noble metals have poor reactivity, conductive particles generated from etching are not easily discharged from an etching chamber. As depicted in FIG. 2, conductive particles 21 may adhere to a side surface of the ferroelectric film 15 and cause a short between the lower electrode film 14 and the upper electrode film 16.
In addition, an etching mask is required to be heat resistant, and a photoresist (resin) cannot be used. Thus, a hard mask composed of an SiO2 film and a TiN film is used in collective etching as described above. In the step of removing the hard mask after the end of etching, however, conductive particles 21 may also be generated and adhere to the side surface of the ferroelectric film 15. The conductive particles 21 adhered to the side surface of the ferroelectric film 15 are difficult to remove even with a drug solution of hydroxylamine or an acid solution or the like.
Patent Document 1 discloses a semiconductor device including a multilayer capacitor. In the semiconductor device, a sidewall is formed on sides of a capacitor insulation film and of an upper electrode film in order to prevent conductive particles generated in etching of a metal film from adhering to the sides of the capacitor insulation film and thus to prevent a short from occurring between the capacitor electrodes. The sidewall is formed by patterning the upper electrode film and the capacitor insulation film, then forming a thick insulation film made of an insulator such as SiO2, Si3N4, Al2O3, TiO3 or Ta2O5 on an entire surface by a CVD (Chemical Vapor Deposition) method, and etching back the insulation film. According to Patent Document 1, adherence of conductive particles is prevented by making a top of the sidewall to have a taper angle of 75° or smaller.
However, in the method described in Patent Document 1, since a thick insulation film is formed on a substrate, and a sidewall is formed by etching back the insulation film, it is difficult to determine the time to finish etching. Thus, overetching may cause chipping or stripping of the sidewall or the upper electrode film. In addition, there is also a problem that the method described in Patent Document 1 requires the taper angle of the top of the sidewall to be 75° or smaller, which results in an increase in thickness of the sidewall and thus makes it difficult to achieve high integration of the semiconductor device.
Furthermore, in Patent Document 1, the sidewall is made by covering a ferroelectric capacitor with an insulation film formed by the CVD method and etching back the insulation film. However, when the insulation film covering the ferroelectric capacitor is formed by a normal CVD method (such as a plasma CVD method or a thermal CVD method), the properties of ferroelectric capacitors may degrade due to hydrogen gas contained in a CVD gas, and heating, or plasma damage in the plasma CVD method. In addition, although Patent Document 1 discloses an example in which the sidewall is made of SiO2 or TiO2, there is another problem that the sidewall made of SiO2 has such low barrier properties to hydrogen or moisture that the capacitor easily deteriorates in etching processing. Furthermore, there is yet another problem that when a ferroelectric capacitor is coated with a TiO2 film, Ti is dispersed in PZT and the properties of PZT may deteriorate.
There is another related technique described in Patent Document 2 considered as related to the embodiments. Patent Document 2 describes etching of a ferroelectric film under specific conditions using high-temperature BCl3 in forming a capacitor of FeRAM with use of a hard mask. Patent Document 2 states that etching with use of the high-temperature BCl3 under the specific conditions can prevent conductive particles generated in etching of a lower electrode film from accumulating on a side surface of the ferroelectric film, which in turn allows prevention of a leak and a short of the ferroelectric capacitor.
In addition, Japanese Patent Application No. 2004-55319 filed by the present applicant discloses FeRAM having a structure in which: multiple lower electrodes are collectively covered with a ferroelectric film; upper electrodes opposed to the respective lower electrodes are formed on the ferroelectric film; and multiple capacitors each composed of the lower electrode, the ferroelectric film, and the upper electrode are covered with a protective film.    Patent Document 1: Japanese Patent No. 3666877    Patent Document 2: Japanese Laid-open Patent Publication No. 2003-318371